The inventive concepts described herein are generally related to a method of applying a wire voltage to a semiconductor device, and more particularly to a method of applying a wire voltage to a semiconductor device in a way that reduces leakage current of the semiconductor device.
Semiconductor memory devices, which store data, are largely categorized into volatile memory devices and non-volatile memory devices. Volatile memory devices lose stored data upon removal of the power supply, while non-volatile memory devices retain stored data upon removal of the power supply. Non-volatile memory devices may be categorized as electrically erasable programmable read-only memories (EEPROMs), flash memories, and so on, and flash memories may be categorized as NOR flash memories and NAND flash memories.
Some of such semiconductor memory devices may perform a programming operation by applying a high voltage to a memory cell. With the recent increase in integration density of semiconductor devices, leakage current may flow between regions of the semiconductor devices. A parasitic transistor may be formed by wires such as a conductive gate to which a high voltage required for a memory cell programming operation is applied, and by active regions surrounding the conductive gate to which the high voltage is applied, and thus leakage current may occur.